The present invention relates to a wafer-level process for fabricating semiconductor planar devices such as diodes and, more particularly, concerns a simplified wafer level process for fabricating planar diodes from semiconductor.
Diodes are mass produced in great numbers every year. As a high volume component found in virtually every electrical device of any complexity, the market for diodes is very large, competitive, and sensitive to pricing pressure. Manufacturers must produce these devices both with sufficient reliability and low cost to satisfy the competitive demands of the marketplace. Currently, one known process for manufacturing diodes from semiconductor chips entails the use of several photolithographic steps employing a mask, each of which increases the cost of manufacture.
A specific example of one such known process is a standard glass passivated pallet process employing three masking steps, and is illustrated in the process flow diagram of FIG. 1. Beginning in step 1 with a wafer of silicon 10, the wafer is doped in step 2 so as to provide P+, N, and N+ regions (respectively indicated as 12, 14, and 16 in FIG. 1). Prior to the first photolithographic step 3, a protective oxide layer is provided in the form of an oxide coating 18. After baking, developing, and hard baking, a first mask is used to generate the structure shown in the figure after step 3, in which windows 19 are opened up in the oxide layer 18. In step 4 these windows are etched to form grids in the silicon wafer, defining the intended boundaries of each diode.
In step 5, a layer 20 of polynitride is deposited to prepare the surface for step 6, the second photolithographic step in which a mask is employed. Here, a layer of glass powder 22 is deposited along the grid as indicated, baked under high pressure and fired (step 7).
In step 8, a low temperature oxide chemical vapor deposition process is used to overlay an oxide (silicon dioxide) on the surface to protect the glass for step 9, the third photolithographic step in which a mask is employed (here to deposit a polymer coating).
Contact etching and photoresist etching is performed in step 10, exposing the P+ and N+ surfaces, which are then coated with nickel plating in step 11 to provide ohmic contacts.
This known process requires three photolithographic steps in which a precision mask is employed. The repeated use of masks and the care with which they must be used is a substantial component in the cost of the finished product produced by this process.
Demand persists for diodes that can be manufactured using simpler and cheaper processes